Nowadays, the read-only-memory (ROM) has been used in all kinds of digital products because it can save data permanently as the power is turned off, and has an only-read function without needing random-access program code, such as the basic-input-output-system (BIOS) in a personal computer.
Please refer to FIG. 1(a) which is a top view of a structure of a mask ROM with a conventional flat cell. The bit line 10 is disposed along the first direction 101 and is composed of a buried layer structure. A gate conducting layer formed by a tungsten silicide (WSix) layer 111 and a polysilicon layer 112 is formed along the second direction 102 to serve as a word line 11. Please refer to FIG. 1(b) and FIG. 1(c) which are sectional views of a mask ROM, taken along line A-A' and line B-B' respectively. There is a gate oxide layer 13 formed between the substrate 12 and the polysilicon layer 112, and a photoresist layer 14 is deposited over the mask ROM. The photoresist layer 14 is patterned by photolithography to define the code implantation area 15 and then impurities are doped into the substrate 12 by an ion implantation process for threshold voltage adjustments.
In an ordinary two-level mask ROM for saving binary digital data, the ion implantation process is performed once to distinguish two different threshold voltages (have and haven't been ion implanted in MOS). However, in order to increase the accumulation density in a memory device, the multi-level mask ROM is developed for storing more data in the same device number and same area of MOS. The multi-level mask ROM is made by executing the ion implantation process several times to distinguish the different threshold voltages. Please refer to FIG. 1(b) and FIG. 1(c). By implanting different ion concentration in different code implantation areas, different areas with different threshold voltages are formed. For example, a three-level mask ROM, formed by two times of ion implantation process, has three different areas with three different implantation concentration. Thus, the multi-level logic in a memory cell can fully utilize the device area and save more data without increasing the device number.
However, in conventional processes, ions must be implanted through a thick gate conducting layer 11 which is formed by a WSix layer 111 and a polysilicon layer 112. The thickness of the WSix layer is ranged from 1000 .ANG. to 1500 .ANG. and so is the polysilicon layer. Therefore, high energy is needed for doping impurities into the substrate 12. The more the energy is needed to penetrate the gate conducting layer, the more serious the ion scattering effect and the ion concentration variation will be. This serious ion concentration variation makes the threshold voltage of the ion implantation area imprecise. The threshold voltage distribution is in the form of Guass distribution as shown in FIG. 2. The ion scattering effect causes the threshold voltage overlap. In a multi-level mask ROM, the problem of the overlap is especially serious. To avoid the overlap, the spaces between each threshold voltage should be increased but the number of the threshold voltage will be limited. In other words, the multi-level mask ROM can not save too many data by the applicant. The present invention is tried to deal with the above situation encountered by the prior art.